Wafer EDS Test Service

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Wafer EDS(Electrical Die Sorting) Test

์ „๊ธฐ์  ํŠน์„ฑ ๊ฒ€์‚ฌ๋ฅผ ํ†ตํ•œ ์–‘ํ’ˆ/๋ถˆ๋Ÿ‰ํ’ˆ ์„ ๋ณ„ ๊ณผ์ • ์ง„ํ•ธํ•œ๋‹ค. ๋˜ํ•œ ์—ฌ๊ธฐ์„œ ๋‚˜์˜จ ์ •๋ณด๋กœ ํ”ผ๋“œ๋ฐฑ์„ ์‹ค์‹œํ•˜๊ณ , ์ˆ˜์œจ ๊ฐœ์„  ์—ฐ๊ตฌ๊ฐ€ ์ง„ํ–‰๋œ๋‹ค.

ํ”„๋กœ๋ธŒ ์นด๋“œ(Probe card)์— ์›จ์ดํผ๋ฅผ ์ ‘์ด‰์‹œ์ผœ์„œ ์ง„ํ–‰ํ•˜๋ฉฐ, ํ”„๋กœ๋ธŒ ํ•€(Probe Pin)์ด ์›จ์ดํผ์™€ ์ ‘์ด‰ํ•ด ์ „๊ธฐ๋ฅผ ๋ณด๋‚ด๊ณ  ๊ทธ ์‹ ํ˜ธ๋ฅผ ํ†ตํ•ด ๋ถˆ๋Ÿ‰์นฉ์„ ์„ ๋ณ„ํ•œ๋‹ค.

์ผ๋ฐ˜์ ์œผ๋กœ Wafer EDS ํ…Œ์ŠคํŠธ๋Š” 4๋‹จ๊ณ„๋กœ ์ง„ํ–‰๋œ๋‹ค.

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Final Test

Final Test


Final Test๋Š” ์ผ๋ จ์˜ ์ œ์กฐ๊ณต์ •(ํšŒ๋กœ์„ค๊ณ„ → Foundry(Fab Process) → EDS → Package Assembly)๋ฅผ ๊ฑฐ์ณ ์ œ์ž‘๋œ ํŒจํ‚ค์ง€๋ฅผ ์”Œ์šด ๋ฐ˜๋„์ฒด์— ๊ฐ Chip(์ œํ’ˆ)์˜ Test ์กฐ๊ฑด์ด ์ž…๋ ฅ๋œ ์žฅ๋น„(TESTER)๋ฅผ ํ†ตํ•ด

์ „์••์ด๋‚˜, ์ „๋ฅ˜, Signal(์ „๊ธฐ ์‹ ํ˜ธ), ์˜จ๋„ ๋“ฑ์˜ Stress๋ฅผ ๊ฐ€ํ•จ์œผ๋กœ์จ Chip(์ œํ’ˆ) ์˜ ์ „๊ธฐ์  ํŠน์„ฑ,

๊ธฐ๋Šฅ์  ํŠน์„ฑ ๋ฐ Chip(์ œํ’ˆ) ์˜ ๋™์ž‘ ์†๋„ ๋“ฑ์„ ๊ฒ€์‚ฌํ•˜์—ฌ ์–‘ํ’ˆ๊ณผ ๋ถˆ๋Ÿ‰์„ ๊ตฌ๋ถ„ํ•˜๋Š” ๊ณต์ •

DC Parameter Test


Chip(์ œํ’ˆ)์˜ ์ „๊ธฐ์  ํŠน์„ฑ์„ ์ธก์ •ํ•˜๋Š” Test(Open/Short Test),

Leakage Test(์ž…์ถœ๋ ฅ Pin), Current Test(Standby / Operation Current) ๋“ฑ์ด ์ง„ํ–‰๋จ

Dynamic Function Test


๋ชจ๋“  Cell์ด ์ •์ƒ์ ์œผ๋กœ ๋™์ž‘ํ•˜๋Š”์ง€ ์ฆ‰ Chip(์ œํ’ˆ)์˜ ๊ธฐ๋Šฅ์„ Testํ•˜๋Š” ๊ฒƒ์œผ๋กœ

Timing Parametric, In/Out Signal Level, Address Enable ๋ฐฉ๋ฒ•, Pattern ๋“ฑ์„ ํ†ตํ•ด Testํ•จ.


Low Power Test


Chip(์ œํ’ˆ) ๋™์ž‘ ์‹œ ์†Œ๋ชจ๋˜๋Š” ์ „๋ฅ˜, Data์˜ ์ €์žฅ ๋Šฅ๋ ฅ์— ์˜ํ•œ Refresh ์ฃผ๊ธฐ ๋“ฑ์„ ๊ฒ€์ฆํ•˜์—ฌ

Device์˜ ์†Œ๋ชจ์ „๋ ฅ์„ Testํ•จ

#2720, Sambo Techno Tower, 122, Jomaru-ro 385beon-gil, Wonmi-gu, Bucheon-si, Gyeonggi-do, 14556, Korea

Tel. 070-4349-0077  l  Fax. 02-6280-2023

E-mail. rootsemi@rootsemicon.co.kr


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